Computer Science and Engineering Graphic ITEB Link    
University of Connecticut Logo
About Computer Science and Engineering
Line
Computer Science and Engineering Undergrad
Line
Computer Science and Engineering Graduate Programs
Line
Computer Science and Engineering Research Programs
Line
Computer Science and Engineering Faculty Information
Line
Computer Science and Engineering Job Opportunities
Line
Computer Science and Engineering News
Line
Computer Science and Engineering Contact Information
Line
School of Engineering Website
Line
University of Connecticut Main Page
Line
Computer Science and Engineering Site Map
Line

Computer Science & 
Engineering Department 
371 Fairfield Road 
Unit 2155 
Storrs, CT 06269-2155 
Phone: (860) 486-3719 
Fax: (860) 486-4817 



Colloquia, Seminars and Conference News

Title : Designing Noise-Tolerant Logic Circuits based on Probabilistic Computation

Date : November 15, 2006. (2:00 pm) Tea starts half an hour before each seminar

Location: ITEB 336

Speaker : Prof. R. Iris Bahar

Abstract:

As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach, whether computing is completely CMOS-based or not. In this talk, I will describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational and sequential circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. While the experimental work is all CMOS-based, our approach could prove essential for any alternative digital logic technology, since defective devices, noise, and restricted power supplies are unavoidable constraints for all envisioned alternatives at the end of the CMOS Roadmap.

Bio:Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. From 1987 to 1992, Prof. Bahar was with Digital Equipment Corporation, working on hardware processor implementation. Since 1996, she has been with the Division of Engineering, Brown University, in Providence, RI, where she is currently an Associate Professor. Her research interests include computer architecture; computer-aided design for synthesis, verification, and low-power applications; and design, test, and reliability issues for nanoscale systems.

[Back]