Colloquia, Seminars and Conference News
Title : SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications
Date : April 24, 2009. (2:00 pm) Tea starts half an hour before each seminar
Location: ITEB 336
Speaker : Xinming Huang
Abstract:
Advanced defense and security applications require integrated microsystems with both power efficiency and reconfigurability. Real-time space-time array processing (STAP), for example, requires hundreds of billion operations per second (GOPS) with a power budget of a few watts. At the same time, reconfigurability is needed to follow evolving algorithms, to support multiple radio frequency interfaces, and to dynamically provide computing resources for changing battlefield situations. Many data streaming applications in the commercial world also have similar needs.
Conventional integrated circuit solutions can provide power efficiency or reconfigurability, but are unable to provide both at the same time. A hardwired Application-Specific Integrated Circuits (ASIC) can provide superior power efficiency but offers little if any flexibility. Alternatively, Field-Programmable Gate Array (FPGA) is the dominant reconfigurable platform for high performance signal processing but it consumes about 10~30 times more power than an ASIC implementation. This research is aimed to bridge the gap between FPGA and ASIC on power efficiency.
In this talk, I will present a new coarse-grained reconfigurable architecture (CGRA), namely SmartCell, which tiles 64 processing elements onto a single chip with reconfigurable interconnections. SmartCell is able to provide stream processing capacity to achieve both performance and power efficiency for a wide range of applications. It can be configured to operate in various computing styles such as SIMD, MIMD, and systolic array fashions. The processor is designed using TSMC 130nm technology with a chip area of 8.2mm2 and power consumption of 160mW at 100MHz. The chip performance is evaluated using a set of benchmark applications. The results show that the power consumption of SmartCell is about 4 times less than the FPGA designs. In addition, SmartCell can provide 2~4 times more throughput when comparing with other existing CGRAs for stream-processing applications.
Bio:Xinming Huang is an Assistant Professor of the Department of Electrical and Computer Engineering at Worcester Polytechnic Institute (WPI). He received his Ph.D. in Electrical Engineering from Virginia Tech on December 2001. After completion of his Ph.D., he joined the Wireless Advanced Technology Laboratory, Bell Labs of Lucent Technologies. In July 2006, he joined the faculty of WPI, where he leads the Embedded Computing Laboratory. He was among the recipients of the Central Bell Labs Annual Excellence Award in 2002, the IBM Faculty Fellowship Award in 2004, and the DARPA Young Faculty Award in 2007. His current research interests are in the areas of circuits and systems design for reconfigurable computing, wireless communications, and cognitive radio networks. He is a member of IEEE and of ACM.
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