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CSE Colloquium: Yan Gu
February 26, 2019 @ 11:00 am - 12:00 pm UTC-5
Presenter: Yan Gu, Postdoc, Carnegie Mellon University
Date: Tuesday, February 26
Location: HBL Video Theater 2, Room 2119
Efficient Algorithms for Modern and Future Architecture
In today’s data-driven world with rapidly increasing data sizes, performance has become more important than ever before. Many new hardware technologies have been designed to store, process, and discover knowledge from ever-growing large-scale data, bringing up new architectural concerns in designing efficient algorithms. However, the simplicity in algorithms and the ease in programming should not be sacrificed for improving performance. In this talk, I will introduce my research on designing algorithms adaptive to modern and future architecture, with simplicity and high performance.
In the first part of this talk, I will focus on the shared-memory parallel setting. I will discuss some general techniques yielding simple parallel algorithms that are efficient both in theory and in practice. The second part of this talk will focus on future platforms for non-volatile main memories (NVMs) that have the special property that writes are more expensive than reads. This property proposes the need for write-efficient algorithms that uses writes significantly fewer than classic approaches. In this talk, I will show how this challenge can be theoretically modeled, and the new algorithms that have good theoretical guarantees as well as better experimental performance. Finally, I will conclude the talk by sketching the future image of computing and directions for algorithm design to accommodate such trends.
Yan Gu is a postdoctoral associate at MIT CSAIL. Prior to that, he received his PhD from Carnegie Mellon University in 2018 advised by Guy Blelloch, and Bachelor’s degree from Tsinghua University in 2012, both in the Computer Science Department. His research designs theoretically-efficient algorithms with good performance in practice, with an emphasis on parallelism and future non-volatile main memories.