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Ph.D. Defense: Abdulrahman Alshegaifi
March 12, 2020 @ 12:30 pm - 1:30 pm UTC-5
Title: Energy-Efficient Cache Architecture Towards Extreme-Scale Computing Systems
Ph.D. Candidate: Abdulrahman Alshegaifi
Major Advisor: Dr. Chun-Hsi Huang
Associate Advisors: Dr. Reda A. Ammar, Dr. Sanguthevar Rajasekaran
Date/Time: Thursday, March 12, 2020 12:30pm
Location: MCHU 307
Abstract:
As we approach the era of exascale systems, where 1,000-core can be integrated in one die, energy efficiency is the most considerable impediment. Future exascale systems that are capable of executing a thousand times as many operations per second as those by current petascale systems are constrained by a power budget of 20MW. A representative current supercomputer typically consumes 17.8 MW. Achieving exaflop performance with nearly the same power of today’s supercomputers is a major research challenge and will force a radical change in all levels of the computing stack, including circuits, hardware architectures, software, and applications. One key contributor to processor energy consumption is the cache. Caches are among the main components in processors, and they play an important role in bridging the speed gap between CPU and main memory. This dissertation investigates an energy-efficient cache architecture towards extreme-scale computing systems. Specifically, we investigate an L1 data cache design that allows to save energy without sacrificing the performance. Since cache design is based on the principle of locality, we start by researching the data locality of two memory regions, i.e. stack and non-stack. Accordingly, we propose a high-performance non-unified data cache architecture, and evaluate the performance of the proposed non-unified data cache design in comparison to that of a conventional unified data cache. Subsequently, we investigate the energy savings of the non-unified cache architecture. Finally, we investigate the effects of replacement policies for this non-unified design in order to further optimize the overall performance of the proposed cache architecture.
