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Ph.D. Defense: Hamza Omar
July 30, 2020 @ 4:00 pm - 5:30 pm EDT
Dissertation Title: Dynamic Hardware Isolation for Efficient Resiliency and Security in Multicore Architectures
Student: Hamza Omar
Major Advisor: Omer Khan
Associate Advisors: Marten van Dijk and John Chandy
Date/Time: Thursday, Jul 30, 2020 4:00 pm | 1 hour 30 minutes | (UTC-04:00) Eastern Time (US & Canada)
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Abstract: Multicore processors are progressively deploying safety-critical applications that demand an efficient, secure, and resilient execution environment to satisfy the safety standards and real-time constraints. However, the concurrent execution of these applications promote space-time sharing of hardware resources (such as on chip core, caches, networks, and memory components), resulting in interference across applications. Hardware interference induces non-deterministic and unpredictable performance trends as applications tend to compete for utilizing these resources. In addition to diminished resiliency guarantees, the interference effects open up numerous side channels for adversaries to leak confidential information, essentially hurting processor security guarantees. This dissertation proposes a novel multicore architecture that incorporates a novel strong isolation principle in hardware to construct strongly isolated clusters of cores, where each cluster is provided with its own dedicated set of core-level resources. It guarantees applications with no destructive interference, resulting in an efficient and effective execution environment for resiliency and security. The proposed architecture implements dynamic hardware isolation, a mechanism where clusters are allowed to dynamically reconfigure their core-level resources to adapt the performance variations among deployed applications. Consequently, load-balanced execution of concurrent applications improves overall system utilization and throughput while assuring strong security and resiliency guarantees. The proposed architecture is prototyped and evaluated on a real Tilera TileGx-72 multicore processor, exhibiting its effectiveness.
