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CSE Colloquium: Shuaiwen Leon Song
March 12, 2019 @ 11:00 am - 12:00 pm UTC-5
Speaker: Shuaiwen Leon Song
Date: March 12
Location: HBL Video Theatre 2
Title: Unleashing the Power of Holistic System Design for Modern Emerging Workloads
Within a decade, the technological underpinnings for the process Gordon Moore described will likely come to an end as silicon photolithography approaches atomic scale. To continue the rapid, predictable, and affordable scaling of computing performance, major vendors have shown increased reliance on heterogeneous hardware acceleration, where multiple novel technologies are integrated into a single heterogeneous system, including different types of accelerators, new memory technologies and fast hybrid interconnect. Under such extreme heterogeneous environment, system design without carefully examining opportunities and complexity from various hardware and software stacks will no longer provide optimal efficiency. In this talk, I will showcase my recent research on applying novel holistic system design strategies to address some of the most challenging issues of two high-impact use cases: highly-interactive virtual reality system design and training for deep non-linear neural models under resource constraints. These two interesting cases have both technical value and significant social impacts, and they have been widely applied in domains such as education, scientific simulation, health care and manufacturing. After the technical discussion, I will talk about some potential research directions and how I connect my research to UConn CS.
Shuaiwen Leon Song is currently a senior staff scientist and technical lead in High Performance Computing Group at Pacific Northwest National Lab (PNNL). He received his Ph.D. in Computer Science from Virginia Tech in July 2013. Prior to joining PNNL in 2013, he has worked with several government and industrial labs including Center for Advanced Computing (CASC) at Lawrence Livermore National Lab (LLNL), Performance Analysis Lab (PAL) at Pacific Northwest National Lab (PNNL), and the Architecture Research Division at NEC Research America at Princeton. He is a recipient of 2011 Livermore ISCR scholar, 2011 Paul E. Torgersen Excellent research award, 2015/2016 PNNL PCSD outstanding performance award, 2018 Pathway to Excellence Achievement award, two Supercomputing best paper nominations (2015 and 2017) and a 2017 HiPEAC paper award. In 2017, he has been honored with IEEE TCHPC early career award at Supercomputing’17 conference. He has published in several major HPC and system architecture conferences including ASPLOS, MICRO, HPCA and Supercomputing. Some of his research has been featured in U.S. Department of Energy research spotlights as well as other media outlets. He has served as organizing or program committee for leading HPC and system architecture venues including SC, PACT, HPDC, PPoPP and ASPLOS. His past and current research are funded by government agencies including DOE Office of Science ASCR, DoD, DARPA and Lab LDRD. He also has strong collaboration with several U.S. Universities and industrial labs including Intel, NVIDIA research and Microsoft Research. He is currently leading two DOE Lab LDRD projects on future complex system design and data-model convergence.